As device feature size decreases in complimentary metal oxide semiconductor (CMOS) integrated circuit (IC) processes, electric fields generated across junctions within a CMOS device can increase as a power supply voltage provided to the CMOS device remains constant. The same increase in electric field also can occur across oxide layers within CMOS processes, e.g., gate oxides, as oxide layers decrease in thickness. When large enough, electric fields can damage junctions and oxide layers within a CMOS device. Additionally, large electric fields can degrade performance parameters of the CMOS device. To prevent damage to CMOS devices as device feature size is reduced, the maximum voltage potential applied to a CMOS device must be scaled downward. Accordingly, the voltage potential of a power supply provided to an IC with reduced device feature size must be decreased.
Another reason for reducing the voltage potentials of IC power supplies relates to the low power consumption requirements for ICs implemented within battery powered devices. For example, reducing power supply voltages to an IC within a laptop computer can reduce the power consumption of the IC. The reduced power consumption of the IC can extend battery life of the laptop computer.
While reducing the voltage potential of a power supply powering internal IC devices can be beneficial to IC device reliability and power consumption, at the circuit board or system level, the IC still may be coupled to components operating with higher power supply voltages. In that case, the IC may operate with two or more power supplies. Each power supply can provide a different voltage potential to the IC. Typically, one or more low voltage power supplies can be provided to power CMOS devices that drive internal circuits of the IC. One or more high voltage power supplies can be provided to power CMOS devices that receive signals from and/or send signals to, circuits external to the IC. For example, an IC can be provided with a 1.3V power supply for internal circuits and a 3.3V power supply for devices coupled to circuits external to the IC.
Circuits powered by power supplies with differing voltage potentials can output signals with different voltage ranges. For example, one digital circuit powered by a 1.8V power supply can output a signal that varies between 0-1.8V, while another digital circuit powered by a 3.3V power supply may output a signal that varies between 0-3.3V. The difference in signal levels between the two digital circuits can create problems at any interface between the two digital circuits.
For example, consider an interface where a CMOS inverter provides a maximum input voltage of 1.8V to a CMOS inverter operating at 3.3V. The 1.8V input typically cannot disable a pull-up P-type field effect transistor (PFET) device within the CMOS inverter, as −1.5V of gate terminal to source terminal voltage, i.e., 1.8V-3.3V, is being applied to the PFET device. A voltage of −1.5V, however, is sufficient to enable the PFET device. With 1.8V applied to the input of the 3.3V CMOS inverter, both the pull-up PFET device and a pull-down NFET device of the 3.3V CMOS inverter can be enabled simultaneously. In that case, the 3.3V CMOS inverter has an open current path from the 3.3V power supply to ground when receiving a static input high of 1.8V. As such, the 3.3V CMOS inverter unnecessarily consumes power when in a static state.